Without limiting the scope of the invention, its background is described in connection with the manufacture of silicon wafers, as an example.
Heretofore, in this field, a series of wet chemical washing steps follow the deposition of operative layers on silicon wafers. In the process for fabricating modern semiconductor integrated circuits, it is necessary to form conductive lines or other structures above previously formed structures. It has been found that irregularities on the wafer surface may be caused by impurities in wet chemical washing steps, which lead to irregularities during the deposition of subsequent layers.
The irregularities caused by the outplating of ions, such as metallic or organic ions, can easily result in incomplete coverage, breaks in the deposited material, or voids when a subsequent layer is deposited directly over the aforementioned highly irregular surfaces. Outplating occurs when ions, normally metallic or organic, leach out from a wash solution, such as hydrofluoric acid, and become deposited on a silicon substrate. Even trace levels of outplated impurities can lead to degradation of minority carrier lifetime leading to a premature breakdown of gate oxide layers.
Unfortunately, these irregularities can not be alleviated at the next major processing step, because it is assumed that the top surface topography of the surface is at its cleanest following a washing step. These irregularities will tend to become even more pronounced as subsequent layers are deposited, causing further problems as the layers stack up in the subsequent processing of the semiconductor structure.
Depending upon the types of material used and their intended purposes, numerous undesirable characteristics are produced when these outplating irregularities occur. Incomplete coverage of an insulating oxide layer can lead to short circuits between metalization layers. Likewise, voids may trap air or processing gases, either contaminating further processing steps, creating weak spots in the film or simply lowering overall device reliability. Sharp points on conductors may result in unusual, undesirable field effects and high current densities. One problem that is widely recognized in the wafer manufacturing process is that, in general, processing high density circuits over highly irregular structures can lead to very poor yields and device performance.
Consequently, it is necessary to insure the integrity and purity of the wet chemicals used in the washing steps in order to facilitate the processing of multi-layer integrated circuits and to improve their yield, performance, and reliability. In fact, all of today's high-density integrated circuit fabrication techniques make use of wet chemical washing steps prior to the deposition of new gate oxide structures at critical points in the fabrication process.
Impurities in wet chemicals have been identified by monitoring the yield of silicon chips derived from a silicon wafer. During the fabrication of very large scale integrated circuits, for example, large amounts of wet chemicals are used in the washing steps that accompany the etching and polishing phases of silicon wafer manufacture prior to a high temperature operation.
It has been found that present methods are unable to detect levels of contamination that lead to wash chemical outplating. Current methods of detecting impurities in washing solutions involve the off-line analysis of samples using, for example, plasma-mass spectroscopy. Among the problems associated with using mass-spectroscopy are lag-time between the time the sample is taken and analyzed, and sensitivity. In addition, plasma-mass spectroscopy is not performed on a daily basis due to the extensive cost of the operation and the waste of resources.
As already mentioned, a significant problem of current monitoring techniques is low sensitivity. The sensitivity of current electrochemical sensors is theoretically limited by the Nernst equation to a maximum sensitivity of 59 mV per decade change in ionic concentration.
Therefore, what is needed is a sensing device that is compatible with silicon wafer fabrication sequences. Furthermore, a need has arisen for an in-line wet chemical contamination monitor that detects impurities beyond the range of electrochemical sensors. Also, there is a need for wafer manufacturing techniques and procedures for use in identifying the onset of wet chemical contamination before a large number of defective silicon wafers are produced due to the undetected contamination.